FPGA Firmware Developer (EP-ESE-BE-2024-190-GRAP)

Job Detail

Job-ID 326665

Job-Beschreibung

Offer DescriptionAbout usAt CERN, the European Organization for Nuclear Research, physicists and engineers are probing the fundamental structure of the universe. Using the world’s largest and most complex scientific instruments, they study the basic constituents of matter – fundamental particles that are made to collide together at close to the speed of light. The process gives physicists clues about how particles interact, and provides insights into the fundamental laws of nature. Find out more onWe are on a Quest. A Journey into discovery like no other. Bring your expertise to our unique work and develop your knowledge and skills at pace. Join world-class subject matter experts on unique projects, in a Quest for greater knowledge and deeper understanding.Begin your CERN Quest. Take Part!Diversity has been an integral part of CERN’s mission since its foundation and is an established value of the Organization. Employing a diverse workforce is central to our success.Job DescriptionYour responsibilitiesAre you ready to work on cutting-edge technology at the forefront of particle physics?Join our team and contribute to the Phase-II upgrade of the Level-1 Central Trigger (L1CT) system for the renowned ATLAS experiment. We’re seeking a talented FPGA Firmware Developer to play a key role in the evolution of our Central Trigger Processor (CTP) and Muon-to-CTP Interface (MUCTPI).Be part of an ambitious initiative to completely redesign the existing VMEbus-based L1CT system. The upgraded system will feature advanced technologies, including:

State-of-the-art hardware based on the AdvancedTCA (ATCA) standard.
Cutting-edge high-density optical links and high-performance FPGAs (AMD/Xilinx Ultrascale+).
Embedded control system using ARM processor-based System-on-Module technology.

As a key contributor, you’ll:

Focus on firmware development for the MUCTPI and CTP modules.
Design, implement and validate complex firmware using HDL simulation tools and in-system testing.
Work hands-on with FPGA evaluation boards, the existing MUCTPI ATCA boards, and future CTP prototypes as they become available.

Where to apply WebsiteRequirementsResearch Field Engineering » Electronic engineering Education Level Master Degree or equivalentSkills/QualificationsYour profileSkills

Experience with designing and testing FPGA firmware for AMD/Xilinx FPGA families, such as Ultrascale(+).
Proficient in the use of the VHDL language and experience with the use of FPGA HDL synthesis and implementation tools, in particular, with the AMD/Xilinx Vivado tool.
Experience with developing test benches and the use of HDL simulation tools (e.g. Modelsim, Riviera). Knowledge of a verification framework such as OSVVM would be an asset.
Experience with using and testing high-speed optical links and AMD/Xilinx multigigabit transceivers (MGT).
Good knowledge of the python scripting language.

Eligibility criteria:

You are a national of a

. * You have a professional background in Electronics engineering (or a related field) and have either:

a Master’s degree with 2 to 6 years of post-graduation professional experience;
or a PhD with no more than 3 years of post-graduation professional experience.
You have never had a CERN fellow or graduate contract before.

Additional InformationAdditional commentsAdditional InformationJob closing date: 19.01.2025 at 23:59 hrs CET.Contract duration: 24 months, with a possible extension up to 36 months maximum.Working hours: 40 hours per weekTarget start date: 01-March-2025Job reference: EP-ESE-BE-2024-190-GRAPField of work: Electrical or Electronics EngineeringWhat we offer

A monthly stipend ranging between 6212 and 6828 Swiss Francs per month (net of tax).
Coverage by CERN’s comprehensive health scheme (for yourself, your spouse and children), and membership of the CERN Pension Fund.
Depending on your individual circumstances: installation grant; family, child and infant allowances; payment of travel expenses at the beginning and end of contract.
30 days of paid leave per year.
On-the-job and formal training at CERN as well as in-house language courses for English and/or French.

Work Location(s)Number of offers available 1 Company/Institute CERN Country Switzerland City Geneva GeofieldContact CityMeyrin WebsiteStreetEsplanade des particules 1 Postal Code1217 E-Mailvirginie.galvin@cern.chSTATUS: EXPIREDShare this page